Product Summary

The EPM7128SQC100-15N is a high-density, high-performance PLD. It is based on Altera’s second-generation MAX architecture.

Parametrics

EPM7128SQC100-15N absolute maximum ratings: (1)Supply voltage With respect to ground:–2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)DC output current, per pin:–25mA to 25 mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:150℃ or 135℃.

Features

EPM7128SQC100-15N features: (1)Open-drain output option in MAX 7000S devices; (2)Programmable macrocell flipflops with individual clear, preset,clock, and clock enable controls; (3)Programmable power-saving mode for a reduction of over 50% in each macrocell; (4)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell; (5)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (6)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (7)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (8)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (9)PCI-compliant devices available.

Diagrams

EPM7128SQC100-15N diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
EPM7128SQC100-15N
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