TMS320BC52PZ80

Product Summary

The TMS320BC52PZ80 is a digital signal processors (DSP). The TMS320BC52PZ80 is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the devices. The TMS320BC52PZ80 executes up to 50 million instructions per second (MIPS).

Parametrics

TMS320BC52PZ80 absolute maximum ratings: (1)Supply voltage range, VDD: -0.3 V to 7 V; (2)Input voltage range, VI: -0.3 V to 7 V; (3)Output voltage range, VO: -0.3 V to 7 V; (4)Operating ambient temperature range, TA: -40 to 85℃; (5)Operating case temperature, TC: 0℃ to 85℃; (6)Storage temperature range, Tstg: -55℃ to 150℃.

Features

TMS320BC52PZ80 features: (1)Powerful 16-Bit TMS320C5x CPU; (2)20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation; (3)25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation ; (4)Single-Cycle 16 × 16-Bit Multiply/Add; (5)224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global); (6)2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM; (7)1K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program/Data RAM (SARAM); (8)1K Dual-Access On-Chip Program/Data RAM (DARAM); (9)Full-Duplex Synchronous Serial Port for Coder/Decoder Interface; (10)Time-Division-Multiplexed (TDM) Serial Port; (11)Hardware or Software Wait-State Generation Capability; (12)On-Chip Timer for Control Operations; (13)Repeat Instructions for Efficient Use of Program Space; (14)Buffered Serial Port; (15)Host Port Interface; (16)Multiple Phase-Locked Loop (PLL) Clocking Options; (17)Block Moves for Data/Program Management; (18)On-Chip Scan-Based Emulation Logic Boundary Scan; (19)Five Packaging Options, 100-Pin Quad Flat Package (PJ Suffix); (20)Low Power Dissipation and Power-Down; (21)Modes: 47 mA (2.35 mA/MIP) at 5 V, 40-MHz Clock (Average); (22)High-Performance Static CMOS Technology; (23)IEEE Standard 1149.1?Test-Access Port (JTAG).

Diagrams