XC3S200-4PQG208C

Spartan-3 FPGA, 200K, 208-PQFP, 630MHZ, 1.2V

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Price:: US $10.00~12.00 / piece [Get Latest Price]

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PartNumber:: XC3S200-4PQG208C

Brand:: Xilinx, Inc - Xilinx | Pack: PQFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-03-29

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Part Number:XC3S200-4PQG208C
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Product Summary

The XC3S200-4PQG208C is a Spartan-3 FPGA. It is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The XC3S200-4PQG208C builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions.

Parametrics

XC3S200-4PQG208C absolute maximum ratings: (1)Internal supply voltage relative to GND: –0.5 to 1.32 V; (2)Auxiliary supply voltage relative to GND: –0.5 to 3.00 V; (3)Output driver supply voltage relative to GND: –0.5 to 3.75 V; (4)Input reference voltage relative to GND: –0.5 to VCCO+0.5 V; (5)Voltage applied to all User I/O pins and Dual-Purpose pins relative to GND:–0.5 to VCCO+0.5 V; (6)Voltage applied to all Dedicated pins relative to GND:–0.5 to VCCAUX+0.5 V.

Features

XC3S200-4PQG208C features: (1)Up to 784 I/O pins; (2)622 Mb/s data transfer rate per I/O; (3)18 single-ended signal standards; (4)8 differential I/O standards including LVDS, RSDS; (5)Termination by Digitally Controlled Impedance; (6)Signal swing ranging from 1.14V to 3.45V; (7)Double Data Rate (DDR) support; (8)DDR, DDR2 SDRAM support up to 333 Mbps; (9)Abundant logic cells with shift register capability; (10)Wide, fast multiplexers; (11)Fast look-ahead carry logic; (12)Dedicated 18 x 18 multipliers; (13)JTAG logic compatible with IEEE 1149.1/1532; (14)Up to 1,872 Kbits of total block RAM; (15)Up to 520 Kbits of total distributed RAM; (16)Digital Clock Manager (up to four DCMs); (17)Clock skew elimination; (18)Frequency synthesis; (19)High resolution phase shifting; (20)Eight global clock lines and abundant routing.