AD6620ASZ-REEL

Product Summary

The AD6620ASZ-REEL is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible. As ADCs achieve higher sampling rates and dynamic range, the AD6620ASZ-REEL becomes increasingly attractive to accomplish the final IF stage of a receiver in the digital domain. Digital IF Processing is less expensive, easier to manufacture, more accurate, and more flexible than a comparable highly selective analog stage.

Parametrics

AD6620ASZ-REEL aboslute maximum ratings: (1)Supply Voltage: -0.3 V to +4.5 V; (2)Input Voltage: -0.3 V to VDD + 0.3 V (Not 5 V Tolerant); (3)Output Voltage Swing: -0.3 V to VDD + 0.3 V; (4)Load Capacitance: 200 pF; (5)Junction Temperature Under Bias: +130℃; (6)Storage Temperature Range -65℃ to +150℃; (7)Lead Temperature (5 sec): +280℃.

Features

AD6620ASZ-REEL features: (1)High Input Sample Rate, 65 MSPS Single Channel Real; 32.5 MSPS Diversity Channel Real; 32.5 MSPS Single Channel Complex; (2)NCO Frequency Translation, Worst Spur Better than-100 dBc; Tuning Resolution Better than 0.02 Hz; (3)2nd Order Cascaded Integrator Comb FIR Filter, Linear Phase Fixed Coefficients; Programmable Decimation Rates: 2, 3 to 16; (4)5th Order Cascaded Integrator Comb FIR Filter, Linear Phase, Fixed Coefficients; Programmable Decimation Rates: 1, 2, 3 to 32; (5)Programmable Decimating RAM Coefficient FIR Filter, Up to 130 Million Taps per Second; 256 20-Bit Programmable Coefficients; Programmable Decimation Rates: 1, 2, 3 to 32; (6)Bidirectional Synchronization Circuitry, Phase Aligns NCOs; Synchronizes Data Output Clocks; (7)Serial or Parallel Baseband Outputs, Pin Selectable Serial or Parallel; Serial Works with SHARC, ADSP-21xx, Most Other; (8)DSPs; 16-Bit Parallel Port, Interleaved I and Q Outputs; (9)Two Separate Control and Configuration Ports, Generic mP Port, Serial Port; (10)3.3 V Optimized CMOS Process; (11)JTAG Boundary Scan.

Diagrams